1. Field of the Invention
The present invention relates to a technology for enabling high-speed transmission of signals between a plurality of LSI chips or a plurality of devices or circuit blocks within a single chip, or between a plurality of boards or a plurality of cabinets, and more particularly, to a receiver circuit and a clock recovery circuit that uses a feedback loop type clock signal generating circuit.
2. Description of the Related Art
Recently, the performance of components used in computers and other information processing apparatuses has been greatly improved. In particular, dramatic improvements have been made, for example, in the performance of processors and semiconductor memory devices such as DRAMs (Dynamic Random Access Memories). The improvements in the performance of semiconductor memory devices, processors, and the like have reached the point where system performance cannot be improved further unless the speed of signal transmission between components or elements is increased.
Specifically, the speed of signal transmission between a main storage device such as a DRAM and a processor (i.e., between LSIs), for example, is becoming a bottleneck impeding performance improvement for a computer as a whole. Furthermore, the need for the improvement of signal transmission speed is increasing not only for signal transmission between cabinets or boards (printed wiring boards), such as between a server and a main storage device or between servers connected via a network, but also for signal transmission between chips or between devices or circuit blocks within a chip because of increasing integration and increasing size of semiconductor chips, decreasing supply voltage levels (low-voltage-swing signals), etc.
In order to address the increase in the amount of data transmission between LSIs or between boards or cabinets, signal transmission speed per pin must be increased. This is also necessary to avoid the increase in package cost, etc. due to an increased pin count. Consequently, inter-LSI signal transmission speeds exceeding 1 Gbps have been achieved in recent years, and it is expected that extremely high signal transmission speeds, such as 4 Gbps or even 10 Gbps, will be achieved in the future (three to eight years from now ).
In order to speed up the signal transmission between LSIs, for example, it is required that the receiver circuit operate with accurate timing for each incoming signal (for data detection and discrimination). It is known in the prior art to provide the signal receiver circuit with a clock recovery circuit that uses a feedback loop type clock signal generating circuit in order to generate a clock (internal clock) of such accurate timing. Here, the value of a phase adjusting weight for clock recovery is generated using, for example, a phase comparator which compares the phase of an external input clock with that of the internal clock.
In order to achieve high-speed signal transmission, it is desired to provide a clock recovery circuit and a receiver circuit wherein limit cycle signal amplitude is small and the jitter dependence and signal level dependence of feedback loop characteristics is reduced (to facilitate prediction of the circuit characteristics). Further, in such high-speed signal transmission, the transmitted signal waveform does not arrive as an ideal rectangular wave due to the characteristics of the transmission line, etc. making accurate signal reproduction difficult.
The prior art and its associated problems will be described in detail later with reference to drawings.